High-level Synthesis for Low-power Design
نویسندگان
چکیده
منابع مشابه
High-level Synthesis for Low-power Design
Power and energy efficiency have emerged as first-order design constraints across the computing spectrum from handheld devices to warehouse-sized datacenters. As the number of transistors continues to scale, effectively managing design complexity under stringent power constraints has become an imminent challenge of the IC industry. The manual process of power optimization in RTL design has been...
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Design for low power is becoming today an important issue for all kinds of electronic applications. This paper presents some specific low power design problems, focusing on power estimation at register-transfer level (RT). Power estimation is a very important issue since it has to help the designer or an automatic tool to make the right decisions. The power estimator described in this paper is ...
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Characteristics of the data being processed can be used to reduce the power consumption in the data path of a VLSI circuit by exploiting their relationship with transition activity during highlevel synthesis. Important relationships between fixed-point, two’s complement data characteristics and 0→1 transition activity in static CMOS circuits are presented in this paper. Models for computing tra...
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Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level synthesis stage. However, previous work may suffer from a large circuit area overhead on the clock control logic. In this paper, we present an I...
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ژورنال
عنوان ژورنال: IPSJ Transactions on System LSI Design Methodology
سال: 2015
ISSN: 1882-6687
DOI: 10.2197/ipsjtsldm.8.12